Reducing Energy Usage of NULL Convention Logic Circuits using NULL Cycle Reduction Combined with Supply Voltage Scaling

The NULL Cycle Reduction (NCR) technique can be used to improve the performance of a NULL Convention Logic (NCL) circuit at the expense of power and area. However, by decreasing the supply voltage, the power of the NCR circuit can be reduced. Since NCR has increased performance, it should be possible to reduce supply voltage to decrease overall power while maintaining the original performance of the circuit. To verify this, the NCR circuit was implemented using a 4-bit by 4-bit dual-rail multiplier as the test circuit, which was simulated in ModelSim to ensure functionality, synthesized into a Verilog netlist using Leonardo, and imported into Cadence to perform transistor-level simulation for power calculations. The supply voltage of the duplicate NCR circuits was decreased until the performance matched the design of the original multiplier, resulting in approximately 25% overall lower energy usage.